w2 highly preferred - NO 3rd party agencies or candidates for this opportunity
all resumes to
If you are a national candidate, you will have to fly-out here for an on-site interview on your own expense. BUT once hired, they can work anywhere remotely but would need fly-in once per quarter to Sunnyvale, CA
Title: ASIC Timing Engineer
Duties: STA engineer primarily responsible for chip timing takedown and constraint writing and analysis. Will also assist in the setup and debug of other automated tool flows.
Must be self-starter, have good energy, and positive approach to work
Experience with signoff timing (understanding of functional and test methodologies, OCV, jitter, noise, and foundry recommendations). Has worked in the setup of PrimeTime both interactive and scripted.
Very strong experience writing timing constraints including for high-speed source-synchronous IO interfaces and asynchronous crossings. Should be able to read IP specs and port or write from scratch the STA constraints for 3rd party controller+PHY.
Able to mitigate functional and test timing issues through understanding of STA methodology, RTL design, clocktree topology, etc.
Strong scripting experience - Tcl, Perl, Python, sh
Organized and consistent method when writing timing constraints
Nice to have P&R experience with ICC2
Nice to have CDC experience
Nice to have PTPX, PowerArtist, and/or UPF experience